My research focuses on reconfigurable computing and electronic design automation. I develop reconfigurable and domain-specific architectures and methodologies to accelerate physical design flows, including mapping, placement, and routing. In hardware security, I investigate fabric vulnerabilities to side-channel and fault-injection attacks, develop novel on-chip sensors, and leverage machine learning for side-channel analysis. Beyond research, I am committed to open-source artifacts that make these advances accessible and reproducible, and to dedicated teaching that has been recognized through institutional awards.
Appointments
Scientist, School of Computer and Communication Sciences, EPFL, Switzerland (2016–present)
Visiting Professor, University of Toronto, Canada (Jul 2023–Jan 2024)
External Lecturer, School of Computer and Communication Sciences, EPFL, Switzerland (2014–2016)
Scientific Collaborator, HEIG-VD, Switzerland (2013–2016)
Embedded Systems Architect, Mihailo Pupin Institute, Serbia (2007–2013)
Intern, ELSYS Eastern Europe Electronic Design Center, Serbia (Jun–Aug 2006)
Education
PhD in Electrical Engineering, School of Electrical Engineering, University of Belgrade, Serbia. Thesis: A Method for Designing Domain-Specific Reconfigurable Arrays Thesis
Advisor: Lazar Saranovac (2008–2013)
Advisor: Lazar Saranovac (2008–2013)
Dipl.-Ing. in Electronics and Telecommunication, School of Electrical Engineering, University of Belgrade, Serbia; Completed a five-year program early. GPA: 9.9/10 (2002–2006)
Research Funding
Swiss National Science Foundation, Principal Investigator (2019–present)
Secure FPGAs in the Cloud, ~535 kCHF Link
Swiss National Science Foundation, Principal Investigator (2023–2024)
Towards Next Generation FPGA Architecture and CAD, ~28 kCHFLink
CYD Doctoral Fellowship, awarded to my former PhD student Dina G. Mahmoud (2020–2024)
ADHeS: Attacks and Defences on FPGA-CPU Heterogeneous Systems, ~295k CHF Link
Teaching
Fundamentals of Digital Systems, EPFL, BSc, 7 ECTS (2024–present)
Information, Computation and Communication, EPFL, BSc, 6 ECTS (2019–present)
Computer Architecture 1, EPFL, BSc, 4 ECTS (2016–2023)
Project in System Programming, EPFL, BSc, 2 ECTS (2019–2020)
Programming, EPFL, BSc, 3 ECTS (2013–2018)
Programming 2, HEIG-VD, BSc, 8 ECTS (2016)
Former PhD Students
Dina G. Mahmoud, PhD Thesis (2024)
Ognjen Glamočanin, PhD Thesis (2023)
Evaluating, Exploiting, and Hiding Power Side-Channel Leakage of Remote FPGAs Thesis
Awards and Distinctions
Best Paper Award (Runner Up), FPGA (2026)
Pirayadi et al., Out with LSQs: Custom Circuits for Memory Access Reordering in Dynamic HLS DOI
Teaching Award, EPFL (2025)
Best teacher in the Computer and the Communication Sciences Sections Award
Best Paper Award, FCCM (2025)
Shrivastava et al., "Guaranteed Yet Hard to Find: Uncovering FPGA Routing Convergence Paradox"DOI
Distinguished Reviewer Award, DATE (2025)
Outstanding Reviewer Awards - A Track Award
Best Paper Award Nomination, FPT (2024)
Košar et al., Parallel FPGA Routing with On-The-Fly Net Decomposition, DOI
Best Paper Award Nomination, FPT (2024)
Singer et al., Multiqueue-Based FPGA Routing: Relaxed A* Priority Ordering for Improved Parallelism, DOI
Best Paper Award Nomination, DDECS (2023)
Glamočanin et al., Active Wire Fences for Multitenant FPGAs DOI
Best Paper Award Nomination, FPT (2019)
Seifoori et al., A Machine Learning Approach for Power Gating the FPGA Routing Network DOI
IEEE Senior Member (2019)
Young Scientist Award, ICLP (2016)
Stojilović et al., Lightning Location Systems and Interstroke Intervals: Effects of Imperfect Detection Efficiency, DOI
Best Paper Award, EMC Europe (2016)
Van de Beek et al., Protection strategy against IEMI for wireless communication infrastructures DOI
Teaching Award for Teaching Excellence, School of Computer and Communication Sciences, EPFL (2015)
Young Author Best Paper Award, TELFOR (2012)
Stojilović et al., Design of antenna system for short-range wireless sensor network DOI
Invited Talks and Seminars
Dagstuhl Seminar 22412, Intelligent Security: Is "AI for Cybersecurity" a Blessing or a Curse, Schloss Dagstuhl, Germany (2022)
Organizers: Nele Mentens, Stjepan Picek, and Ahmad-Reza Sadeghi
Navigating Hardware Security Challenges in Reconfigurable Cloud Computing, Women in Circuits Workshop on Hardware Security (collocated with ESSERC), Bruges, Belgium (2024)
Organizers: Ingrid Verbauwhede and Nele Mentens
Speeding Up Commercial FPGA Routing by Decoupling and Mitigating the Intra-CLB Bottleneck, University of Toronto, Canada (2023)
Host: Jason Anderson
Multi-Stage Routing for Next-Gen Commercial FPGAs, ACM/IEEE International Workshop on System-Level Interconnect Pathfinding (SLIP). San Francisco, USA (2023)
Organizers: Mustafa Badaroglu, Shantanu Dutt, and Pascal Vivet
Remote FPGA-Driven Electrical-Level Attacks, Worcester Polytechnic Institute, MA, USA (2023)
Organizer: Shahin Tajik
Organizers: Lejla Batina, Nele Mentens, and Ahmad-Reza Sadeghi
Hardware Trojans and Side-Channel Attacks, CYD Research Day (2021)
Host: Vincent Lenders
Timing Violation-Induced Faults in Multi-Tenant FPGAs, Xi'an University, China (2019)
Host: Wei Hu
Conference and Workshop Organization
Vice General Chair, HEART (2026)
Publicity Chair, FPL (2026)
Program Co-Chair, FPL (2025)
Special Session Co-organizer, ASAP, Reconfigurable Edge Computing (2025)
Track Chair and Co-Chair, DATE, Track A3: Secure Systems, Circuits and Architectures (2024–2025)
Program Co-Chair, ARC (2025)
Publicity Co-Chair, HEART (2024)
Topic Chair, DDECS, Secure HW and Embedded Systems (2023, 2025)
Co-organizer, DAC, Tutorial: Secure Sharing of FPGAs in the Cloud (2022)
Co-organizer, Workshop on Security for Custom Computing Machines (SCCM) (2022–2023, 2025)
Track Chair, VLSID, Track: Architectures (2022)
Co-organizer, DATE, Special Session: When FPGA Turns Against You: Side-channel and Fault Attacks in Sha FPGAs (2021)
PhD Forum Chair, FPL (2016)
Demo Night Chair, FPL (2016)
Editorial Service and Reviewing
Associate Editor, IEEE Transactions on Emerging Topics in Computing (2026–ongoing)
Associate Editor, ACM Transactions on Reconfigurable Technology and Systems (2022–ongoing)
Associate Editor, IEEE Embedded Systems Letters (2022–2024)
Program Committee Member, TCHES [2026], DAC [2025–ongoing]; DATE [2023–ongoing]; FPGA [2021–ongoing], FCCM [2020–2023], FPL [2017–ongoing], OPTIMIST [2024–2025]; MAL-IoT [2019–2021, 2023, 2025]; ASAP [2022]; DDECS [2023], RAW [2020], VLSID [2022]
Journal Reviewing, IEEE TCAD; IEEE TVLSI; IEEE TEMC; IEEE TC; IEEE TPDS; IEEE Access; ACM TRETS; ACM Computing Surveys; IET Circuits, Devices & Systems
Departmental Service
Bourses d'Excellence Committee Member (2025–2026)
Presentation of BSc Programs in IC at Information Days for Bachelor of Science (2026)
Academic Program Coordinator for Study Trip, Barcelona, Spain (2024)
Candidacy Exam Committee Member, Lin Qunyou [2023], Mingfei Yu [2023]
, Participation in the EDIC Open House, faculty candidate interviews, and curriculum development for the computer architecture and systems group
Publications
Conferences
Out With LSQs: Custom Circuits for Memory Access Reordering in Dynamic HLS
🏆 Best Paper Award (Runner Up)
ROBoost: A Study of FPGA Logic-Based Power-Wasting Primitives
Guaranteed Yet Hard to Find: Uncovering FPGA Routing Convergence Paradox
🏆 Best Paper Award
FRIDA: Reconfigurable Arrays for Dynamically Scheduled High-Level Synthesis
FRESCO: Efficient Subgraph Enumeration for Scalable Clustering in Heterogeneous CGRAs
Parallel FPGA Routing With On-The-Fly Net Decomposition
🏆 Best Paper Award Nominee
Multiqueue-Based FPGA Routing: Relaxed A* Priority Ordering for Improved Parallelism
🏆 Best Paper Award Nominee
Temperature Impact on Remote Power Side-Channel Attacks on Shared FPGAs
Active Wire Fences for Multitenant FPGAs
🏆 Best Paper Award Nominee
GRAMM: Fast CGRA Application Mapping Based on a Heuristic for Finding Graph Minors
IIBLAST: Speeding Up Commercial FPGA Routing by Decoupling and Mitigating the Intra-CLB Bottleneck
A Deep-Learning Approach to Side-Channel Based CPU Disassembly at Design Time
FPGA-to-CPU Undervolting Attacks
Shared FPGAs and the Holy Grail: Protections Against Side-Channel and Fault Attacks
NetCracker: A Peek Into the Routing Architecture of Xilinx 7-Series FPGAs
Deep Learning Detection of GPS Spoofing
Are Cloud FPGAs Really Vulnerable to Power Analysis Attacks?
Closing Leaks: Routing Against Crosstalk Side-Channel Attacks
Built-In Self-Evaluation of First-Order Power Side-Channel Leakage for FPGAs
X-Attack: Remote Activation of Satisfiability Don't-Care Hardware Trojans on Shared FPGAs
Nonintrusive and Adaptive Monitoring for Locating Voltage Attacks in Virtualized FPGAs
A Shared-Memory Parallel Implementation of the RePlAce Global Cell Placer
Timing Violation Induced Faults in Multi-Tenant FPGAs
Physical Side-Channel Attacks and Covert Communication on FPGAs: A Survey
A Machine Learning Approach for Power Gating the FPGA Routing Network
🏆 Best Paper Award Nominee
FPGA-Assisted Deterministic Routing for FPGAs
Deterministic Parallel Routing for FPGAs Based on Galois Parallel Execution Model
Parallel FPGA Routing: Survey and Challenges
A Comparator-Based Technique for Identification of Intentional Electromagnetic Interference Attacks
Effects of Mounting Pads and Length Imbalance on Performance of Fast Differential Interconnects
Performance Analysis of Space-Vector Modulated Two- and Three-Level Inverters
802.11b Small-Signal Amplifier Based on the BFG25A/X
Selective Flexibility: Breaking the Rigidity of Datapath Merging
TDoA-Based Localisation of Radiated IEMI Sources
Design of Antenna System for Short-Range Wireless Sensor Network
🏆 Blažo Mirčevski Award
Award
A Cost-Efficient System for Detecting an Intentional Electromagnetic Interference (IEMI) Attack
Analysis of Switching Noise on Power Planes
Evaluation of the Electric-Field Transfer Functions Between IEMI Sources and Banking IT Equipment
The European Project STRUCTURES: Challenges and Results
🏆 Best Paper Award
Influence of LLS Detection Efficiency on the Measured Distribution of Interstroke Intervals
Lightning Location Systems and Interstroke Intervals: Effects of Imperfect Detection Efficiency
🏆 Young Scientist Award
Protection Strategy Against IEMI for Wireless Communication Infrastructures
Development of a Lightning Location System Based on Electromagnetic Time Reversal: Technical Challenges and Expected Gain
Journal Articles
X-Attack 2.0: The Risk of Power Wasters and Satisfiability Don't-Care Hardware Trojans to Shared Cloud FPGAs
Electrical-Level Attacks on CPUs, FPGAs, and GPUs: Survey and Implications in the Heterogeneous Era
The Side-Channel Metrics Cheat Sheet
Instruction-Level Power Side-Channel Leakage Evaluation of Soft-Core CPUs on Shared FPGAs
A Visionary Look at the Security of Reconfigurable Cloud Computing
RDS: FPGA Routing Delay Sensors for Effective Remote Power Analysis Attacks
DFAulted: Analyzing and Exploiting CPU Software Faults Caused by FPGA-Driven Undervolting Attacks
Shrinking FPGA Static Power via Machine Learning-Based Power Gating and Enhanced Routing
Selective Flexibility: Creating Domain-Specific Reconfigurable Arrays
Closed-Form Formulas for Frequency-Dependent Per-Unit-Length Inductance and Resistance of Microstrip Transmission Lines That Provide Causal Response
Quasi-Impulse Response of Frequency-Periodic Microwave Networks
Causal Models of Electrically Large and Lossy Dielectric Bodies
Remote Electrical-Level Attacks on Cloud FPGAs: The Role of AI
Book Chapters
Practical Implementations of Remote Power Side-Channel and Fault-Injection Attacks on Multitenant FPGAs
DOI: 10.1007/978-3-031-45395-3_5
Students' Perception of IT Curricula and Career Opportunities in Serbia and Macedonia
DOI: 10.1007/978-94-6091-982-4_18
Data and Artifacts
Instruction-Level Power Side-Channel Leakage Evaluation of Soft-Core CPUs on Shared FPGAs - Artifacts
RDS: FPGA Routing Delay Sensors for Effective Remote Power Analysis Attacks - Artifacts
IIBLAST: Speeding Up Commercial FPGA Routing by Decoupling and Mitigating the Intra-CLB Bottleneck - Artifacts
MetriSCA
ROBoost: A Study of FPGA Logic-Based Power-Wasting Primitives - Artifacts
Guaranteed Yet Hard to Find: Uncovering FPGA Routing Convergence Paradox - Artifacts
Editorship
Applied Reconfigurable Computing. Architectures, Tools, and Applications: 21st International Symposium (ARC 2025)
DOI: 10.1007/978-3-031-87995-1
Informal and Other Publications
Nonintrusive and Adaptive Monitoring for Locating Voltage Attacks in Virtualized FPGAs
CloudMoles: Surveillance of Power-Wasting Activities by Infiltrating Undercover Sensors
A Method for Designing Domain-Specific Reconfigurable Arrays